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 RF2637
0
Typical Applications * 3V Basestation Systems * General Purpose Linear IF Amplifier * Commercial and Consumer Systems * Portable Battery-Powered Equipment
RECEIVE AGC AMPLIFIER
Product Description
The RF2637 is a complete AGC amplifier designed for the receive section of 3V cellular and PCS applications basestations. It is designed to amplify IF signals while providing more than 90dB of gain control range. Noise Figure, IP3, and other specifications are designed for basestations. The IC is manufactured on an advanced high frequency SiGe process, and is packaged in a standard miniature 8-lead plastic MSOP package.
6 MAX 0 MIN 0.192 + 0.008 0.012 0.006 + 0.003 -A-
0.0256
0.118 + 0.004 sq.
0.034
NOTES: 1. Shaded lead is pin 1. 2. All dimensions are exclusive of flash, protrusions or burrs. 3. Lead coplanarity: 0.002 with respect to datum "A".
0.021 + 0.004
0.006 + 0.002
Optimum Technology Matching(R) Applied
Si BJT Si Bi-CMOS InGaP/HBT GaAs HBT SiGe HBT GaN HEMT GaAs MESFET Si CMOS SiGe Bi-CMOS
Package Style: MSOP-8
Features * Supports Basestation Applications * -55dB to +51dB Gain Control Range @ 85MHz * Single 3V Power Supply * -2dBm Input IP3 * 12MHz to 385MHz Operation
IN+ 1 IN- 2 GND 3 GC 4 GAIN CONTROL
8 VCC1 7 VCC2 6 OUT+
Ordering Information
5 OUTRF2637 RF2637 PCBA Receive AGC Amplifier Fully Assembled Evaluation Board
Functional Block Diagram
RF Micro Devices, Inc. 7628 Thorndike Road Greensboro, NC 27409, USA
Tel (336) 664 1233 Fax (336) 664 0454 http://www.rfmd.com
Rev A3 040511
10-41
RF2637
Absolute Maximum Ratings Parameter
Supply Voltage Control Voltage Input RF Power Operating Ambient Temperature Storage Temperature
Value
-0.5 to +7.0 -0.5 to +5.0 +10 -40 to +85 -40 to +150
Unit
VDC VDC dBm C C Caution! ESD sensitive device.
RF Micro Devices believes the furnished information is correct and accurate at the time of this printing. However, RF Micro Devices reserves the right to make changes to its products without notice. RF Micro Devices does not assume responsibility for the use of the described product(s).
Parameter
Specification Min. Typ. Max.
Unit
Condition
T=25C, 85MHz, VCC =3.0V, ZS =500, ZL =500, 500 External Input Terminating Resistor, 500 External Output Terminating Resistor (Effective ZS =333, Effective ZL =250) (See Application Example)
Overall
Frequency Range Maximum Gain Minimum Gain Maximum Gain Minimum Gain Gain Slope Gain Control Voltage Range Gain Control Input Impedance Noise Figure Input IP3 Stability (Max VSWR)
+40 -65 +35 -68
-46 10:1
12 to 385 +51 -55 +45 -58 57 0 to 2.5 30 5 -40 -2
+65 -40 +55 -48
7.2
MHz dB dB dB dB dB/V VDC k dB dBm dBm
VGC =2.5V, 85MHz VGC =0.1V, 85MHz VGC =2.5V, 385MHz VGC =0.1V, 385MHz Note 1 Source impedance of 4.7k At maximum gain and 85MHz At +40dB gain, referenced to 500 At minimum gain, referenced to 500 Spurious<-70dBm CDMA, differential
IF Input
Input Impedance 1 2.7 to 3.4 10 11.5 k V mA mA C/W C
Power Supply
Voltage Current Consumption 6 7 15 15 Minimum gain, VCC =3.0V Maximum gain, VCC =3.0V Theta J-Ref 85C Ref 85C
Thermal
Thermal Resistance 150 Maximum Junction Temperature 90 Note 1: Measured between a gain control voltage of 1.0V to 1.5V.
10-42
Rev A3 040511
RF2637
Pin 1 Function IN+ Description
CDMA balanced input pin. This pin is internally DC-biased and should be DC-blocked if connected to a device with a DC level other than VCC present. A DC to connection to VCC is acceptable. For single-ended input operation, one pin is used as an input and the other CDMA input is AC-coupled to ground. The balanced input impedance is 1k, while the single-ended input impedance is 500. Same as pin 2, except complementary input. Ground connection. For best performance, keep traces physically short and connect immediately to ground plane. Analog gain adjustment for all amplifiers. Valid control ranges are from 0V to 2.5V. Maximum gain is selected with 2.5V. Minimum gain is selected with 0V. These voltages are only valid for a 4.7k DC source impedance.
Interface Schematic
BIAS
700 CDMA+
700 CDMA-
2 3 4
INGND GC
See pin 1.
VCC
12.7 k 23.5 k 15 k
5
OUT-
6 7
OUT+ VCC2
Balanced output pin. This is an open-collector output, designed to operate into a 250 balanced load. The load sets the operating impedOUT+ ance, but an external choke or matching inductor to VCC must also be supplied in order to correctly bias this output. This bias inductor is typically incorporated in the matching network between the output and next stage. Because this pin is biased to VCC, a DC-blocking capacitor must be used if the next stage's input has a DC path to ground. Same as pin 5, except complementary output. See pin 5. Supply voltage pin. External bypassing is required. The trace length between the pin and the bypass capacitors should be minimized. The ground side of the bypass capacitors should connect immediately to ground plane. Same as pin 7.
OUT-
8
VCC1
See pin 7.
Rev A3 040511
10-43
RF2637
Application Schematic
Measurement Reference Plane
ZS=500 CDMA IF Filter CDMA+ CDMAZ IN, EFF=500
Z S, EFF=333 1 2 Z IN=1 k 3 GAIN 4.7 k 4 GAIN CONTROL 6 R2: 500 5 ZLOAD,EFF=250 C1 L1 VCC C2 OUTMeasurement Reference Plane ZOUT=500 8 7 10 nF VCC L1 ZLOAD=500 C2 OUT+
R1: 1 k
C1
R1 sets the CDMA balanced input impedance. The effective input impedance is then 500 . R2 sets the balanced output impedance to 500 . L1 and C2 serve dual purposes. L1 serves as an output bias choke, and C2 serves as a series DC block. In addition, the values of L1 and C2 may be chosen to form an impedance matching network of the load impedance is not 500 . Otherwise, the values of L1 and C1 are chosen to form a parallel-resonant tank circuit at the IF when the load impedance is 500 .
10 nF
Evaluation Board Schematic
(Download Bill of Materials from www.rfmd.com.)
CDMA J1 SMA
50 strip T1
C3 15 pF C4 15 pF L2 390 nH
L1 390 nH C1 10 nF C2 10 nF R1 1 k 1 2 3 4 GAIN CONTROL 8 7 6 5 L3 390nH C9 15 pF L4 390nH C8 15 pF
C10 10 nF VCC OUT T2 R3 510 50 strip J2 SMA
GC P1 P1-1 1 2 P1-3 3 VCC GND GC R2 4.7 k C5 1 nF
2627400A
VCC C6 10 nF C7 10 nF
10-44
Rev A3 040511
RF2637
Evaluation Board Layout Board Size 2.750" x 2.000"
Board Thickness 0.031", Board Material FR-4
Rev A3 040511
10-45
RF2637
10-46
Rev A3 040511
RF2637
Gain versus VGC Across Temperature,
60.0
Input IP3 versus VGC Across Temperature,
0.0
VCC = 3.0V, FO = 85MHz
VCC = 3.0V
40.0
-10.0
20.0
-20.0
0.0
Input IP3 (dBm)
-40C 25C 85C
Gain (dB)
-30.0
-20.0
-40.0
-40.0
-50.0 -40C 25C 85C -60.0 0.0 0.5 1.0 1.5 2.0 2.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0
-60.0
VGC (V)
VGC (V)
Noise Figure versus Frequency Across Temperature,
9.0 8.0 7.0 6.0 5.0 4.0 3.0 2.0 1.0 0.0 0.0 50.0 100.0 150.0 200.0 250.0 300.0 350.0 400.0 450.0 -40C 25C 85C
VCC = 3.0V, VGC = 2.5V
Noise Figure (dB)
Frequency (MHz)
Rev A3 040511
10-47
RF2637
10-48
Rev A3 040511


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